Japanese Laid-open Patent Application Nos. 2003-023252 and 2003-023253 describe a wiring board with a multilayer wiring formed by buildup technique. According to the buildup technique, formation of an insulating layer, formation of a via hole, and formation of a wiring using electrolytic plating are repeated to form the multilayer wiring.
In response to trend in recent years toward higher performance of an electronic part such as a semiconductor chip, efforts are being made to make a wiring layer of a wiring board finer on which the electronic part is to be mounted.